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TMS320C5515
www.ti.com
SPRS645F – AUGUST 2010 – REVISED OCTOBER 2013
3.7.1.2
MMC1, I2S1, and GP[11:6] Pin Multiplexing [EBSR.SP1MODE Bits]
The MMC1, I2S1, and GPIO signal muxing is determined by the value of the SP1MODE bit fields in the External Bus Selection Register (EBSR)
register. For more details on the actual pin functions, see Table 3-7 .
Table 3-7. MMC1, I2S1, and GP[11:6] Pin Multiplexing
EBSR SP1MODE BITS
PDINHIBR1
REGISTER
BIT FIELDS (1)
S10PD
S11PD
S12PD
S13PD
S14PD
S15PD
PIN NAME
MMC1_CLK/I2S1_CLK/GP[6]
MMC1_CMD/I2S1_FS/GP[7]
MMC1_D0/I2S1_DX/GP[8]
MMC1_D1/I2S1_RX/GP[9]
MMC1_D2/GP[10]
MMC1_D3/GP[11]
MODE 0
00
(Reset Default)
MMC1_CLK
MMC1_CMD
MMC1_D0
MMC1_D1
MMC1_D2
MMC1_D3
MODE 1
01
I2S1_CLK
I2S1_FS
I2S1_DX
I2S1_RX
GP[10]
GP[11]
MODE 2
10
GP[6]
GP[7]
GP[8]
GP[9]
GP[10]
GP[11]
(1)
The pin names with PDINHIBR1 register bit field references can have the pulldown register enabled or disabled via this register.
Copyright ? 2010–2013, Texas Instruments Incorporated
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